In the fabrication of integrated circuits, a number of processes have been established which involve the application of high energy beams onto semiconductor wafers in vacuum. These processes include ion implantation, ion beam milling and reactive ion etching. In each instance, a beam of ions is generated in a source and directed with varying degrees of acceleration toward a target. Ion implantation has become a standard technique for introducing impurities into semiconductor wafers. Impurities are introduced into the bulk of semiconductor wafers by using the momentum of energetic ions as a means of imbedding them in the crystalline lattice of the semiconductor material.
As energetic ions impinge on a semiconductor wafer and travel into the bulk, heat is generated by the atomic collisions. This heat can become significant as the energy level, or current level, of the ion beam is increased and can result in uncontrolled diffusion of impurities beyond prescribed limits. As device geometries become smaller, this uncontrolled diffusion becomes less acceptable. A more severe problem with heating is the degradation of patterned photoresist layers which are applied to semiconductor wafers before processing and which have relatively low melting points.
In commercial semiconductor processing, a major objective is to achieve a high throughput in terms of wafers processed per unit time. One way to achieve high throughput in an ion beam system is to use a relatively high current beam. However, large amounts of heat may be generated in the wafer. Thus, it is necessary to cool the wafer in order to prevent elevated temperatures from being attained.
Techniques for keeping the wafer temperature below a prescribed limit have included batch processing in which the incident power is spread over a number of wafers, time-shared scanning of the beam and conductive cooling through direct solid-to-solid contact between a wafer and a heat sink (see U.S. Pat. No. 4,282,924). The cooling efficiency of systems employing solid-to-solid contact is limited by the extent to which the back side of the wafer contacts the thermally conductive surface, since at the microscopic level, only small areas of the two surfaces (typically less than 5%) actually come into contact.
The technique of gas conduction is known to permit thermal coupling between two opposed surfaces and has been applied to semiconductor processing in vacuum. In one approach, gas is introduced into a cavity between a wafer and a support plate (see U.S. Pat. No. 4,264,762). The achievable thermal transfer with this approach, however, is limited since bowing of the wafer occurs at relatively low gas pressures.
Gas-assisted solid-to-solid thermal transfer with a semiconductor wafer is disclosed in U.S. Pat. No. 4,457,359, assigned to the assignee of the present application. A semiconductor wafer is clamped at its periphery onto a shaped platen, and gas under pressure is introduced into the microscopic void region between the platen and the wafer. The gas pressure approaches that of the preloading, clamping pressure without any appreciable increase in the wafer-to-platen spacing. Since the gas pressure is significantly increased without any increase in the wafer-to-platen gap, the thermal resistance is reduced and solid-to-solid thermal transfer with gas assistance produces optimum results. In both of these approaches, the gas is supplied from a gas source including means for regulating the pressure coupled to the thermal transfer region behind the wafer.
Regardless of the shape of the platen which supports the wafer, it is necessary to limit the flow of gas from the thermal transfer region into the vacuum processing chamber. An uncontrolled leak into the vacuum chamber will cause scattering of the ion beam and neutralizing collisions which can affect dose measurement accuracy. One way of inhibiting the flow of gas from the thermal transfer region is to position an elastomer O-ring in a groove in the platen surface near the periphery of the semiconductor wafer. When the wafer is clamped against the platen surface, the O-ring is compressed, thereby forming a peripheral seal around the thermal transfer region.
While the seal between the elastomer O-ring and the semiconductor wafer is generally satisfactory, it has certain disadvantages. The clamping ring for clamping the wafer against the platen surface is typically as close to the wafer periphery as practical, so that otherwise usable wafer area is not blocked by the clamping ring. The O-ring is located radially inward from the wafer edge and from the clamping ring to avoid overlapping the wafer flat. Thus, when the wafer is clamped in position, the O-ring exerts a force on the wafer which is opposite in direction to the clamping force and radially inward of the clamping force. As a result, the center portion of the wafer tends to be lifted, and the pressure between the wafer and the platen surface in the thermal transfer region is reduced. When lifting occurs, the rate of thermal transfer between the wafer and the platen surface is substantially reduced. Furthermore, the oppositely directed clamping and O-ring forces stress the semiconductor wafer and, in some cases, have overstressed wafers beyond the normally accepted limit of 8,000 psi causing wafer breakage. In addition, the wafer can stick to prior art O-rings, causing a highly undesirable interruption in processing to free the wafer.
In ion implantation systems, the depth of ion penetration into the semiconductor material depends in part on the orientation angle between the crystalline lattice of the semiconductor material and the ion beam. For certain angles, an undesirable effect known as channelling results in excessive ion penetration. When wafers are clamped to a curved or domed platen, the incident angle of the ion beam varies over the wafer surface, resulting in spatially variable channelling. It is desirable to avoid such spatially variable channelling by maintaining a constant angle of incidence between the wafer and the ion beam. However, the clamping and O-ring forces described above tend to deform the wafer into a dome, thereby exacerbating the channelling problem.
It is desirable to provide a means for sealing the thermal transfer region between the wafer and the platen surface without overstressing the wafer and without adversely affecting thermal transfer characteristics. U.S. Pat. No. 4,542,298, assigned to the assignee of the present application, discloses a technique for removal of gas escaping from the thermal transfer region before it reaches the high vacuum chamber. An intermediate region around the periphery of the wafer is vacuum pumped to a pressure below that of the gas in the thermal transfer region. This arrangement is disadvantageous in that a seal is required between the peripheral front surface of the wafer and the high vacuum chamber, thereby complicating the construction of the wafer processing station.
It is an object of the present invention to provide improved apparatus for thermal transfer with a thin, flexible workpiece in a vacuum chamber.
It is a further object of the present invention to provide improved apparatus for thermal transfer with a thin, flexible workpiece in a vacuum chamber wherein a thermal transfer gas is inhibited from reaching the high vacuum region.
It is a further object of the present invention to provide apparatus for thermal transfer with a thin, flexible workpiece in a vacuum chamber without overstressing the workpiece.